1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
Semiconductor integrated circuits, in particular, integrated circuits that use MOS transistors, are becoming more and more highly integrated. As the circuits achieve higher integration, the size of MOS transistors used therein is reduced to a nanometer range. With smaller MOS transistors, it sometimes becomes difficult to suppress leak current and to decrease the area occupied by the circuit since a particular amount of current is required. Under these circumstances, a surrounding gate transistor (hereinafter referred to as SGT), which includes a source, a gate, and a drain arranged in perpendicular to a substrate, the gate surrounding a pillar-shaped semiconductor layer, has been proposed (for example, refer to Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
Using a metal in the gate electrode instead of polysilicon helps suppress depletion and decrease the resistance of the gate electrode. However, this requires a production process that always takes into account metal contamination caused by the metal gate in the steps subsequent to formation of the metal gate.
To produce existing MOS transistors, a metal-gate-last process in which a metal gate is formed after a high temperature process is put into practice so as to avoid incompatibility between the metal gate process and the high temperature process (for example, refer to A 45 nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-free Packaging, IEDM2007 K. Mistry et. al, pp 247-250).
That is, a MOS transistor has been made by forming a gate with polysilicon, depositing an interlayer insulating film on the polysilicon, exposing the polysilicon gate by chemical mechanical polishing (CMP), etching the polysilicon gate, and depositing a metal. In order to avoid incompatibility between the metal gate process and the high temperature process, it is also necessary for producing a SGT to employ a metal-gate-last process with which a metal gate is formed after a high temperature process. Since the upper part of a pillar-shaped silicon layer of a SGT is located at a position higher than the gate, some adjustment must be made in employing the metal-gate-last process.
An existing MOS transistor uses a first insulating film in order to decrease the parasitic capacitance between the gate line and the substrate. For example, in making a FINFET (refer to High performance 22/20 nm FinFET CMOS devices with advanced high-K/metal gate scheme, IEDM2010, CC. Wu, et. al, 27.1.1-27.1.4, for example), a first insulating film is formed around one fin-shaped semiconductor layer and then etched back so as to expose the fin-shaped semiconductor layer and to decrease the parasitic capacitance between the gate line and the substrate. In making a SGT also, a first insulating film is needed to reduce the parasitic capacitance between the gate line and the substrate. Since a SGT includes not only a fin-shaped semiconductor layer but also a pillar-shaped semiconductor layer, some adjustment must be made in order to form a pillar-shaped semiconductor layer.
According to a known SGT manufacturing process, a contact hole for a pillar-shaped silicon layer is formed by etching through a mask and then contact holes for a gate line and a planar silicon layer are formed by etching through a mask (for example, refer to Japanese Unexamined Patent Application Publication No. 2011-258780). That is, conventionally, two masks have been used for forming contacts.